1. Field of the Invention
The invention relates to semiconductor integrated-circuits manufacturing and more particularly to a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits.
2. Description of Related Art
The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a major device for existing very high-density integrated-circuits manufacturing. Basically, there are two kinds of regions for integrated-circuits implementation in a semiconductor substrate: one is the active area and the other is the isolation area. The active area is the exposed semiconductor surface for device fabrication, which is surrounded by the isolation regions having thicker dielectric oxides over the semiconductor surface. The isolation area can be formed by the local oxidation of silicon (LOCOS) as shown in FIG. 1 or by the shallow-trench-isolation (STI) as shown in FIG. 2. In general, the LOCOS isolation needs higher temperature to grow the desired field oxides (FOX) 202a and the bird""s beak having a width xcex94W in each side is formed in the designated active area. Moreover, the doping impurities of the field-encroachment implant 201a used to increase the field threshold-voltage may diffuse into the active area and further decreases the active area, resulting in the so-called narrow-width effects. In addition, the structure surface after forming LOCOS isolation is not planarized, which becomes difficult for fine-line lithography. For the minimum-feature-size smaller than 0.25 xcexcm, the shallow-trench-isolation as shown in FIG. 2 becomes a major trend for deep-submicrometer devices and their integrated-circuits fabrication. Comparing FIG. 1 to FIG. 2, it is clearly seen that the isolation area of using LOCOS is much larger than that of using STI due to the bird""s beak formation and the doping-impurity diffusion of the field-encroachment implant. However, the device structure fabricated in the active area is still the same although the device dimension can be scaled according to the scaling rule based on device physics. For a semiconductor device in the channel-length direction (A-Axe2x80x2) as shown in FIG. 2B, there are a thin gate-oxide layer 302 formed on a semiconductor substrate 100, a highly-conductive gate layer 303a on a thin gate-oxide layer 302, a capped dielectric layer 304a over the highly-conductive gate layer 303a, two dielectric spacers 306a formed along the sidewalls of the formed gate structure, two lightly-doped source and drain regions 305a, two heavily-doped source and drain regions 307a, two silicided regions 308a for source and drain contacts, two barrier-metal layers 310a, two plug-metal films 311a and two metal layers 312a for interconnect. As shown in FIG. 2C for the channel-width direction (B-Bxe2x80x2), it is quite clear that the shallow-trench-isolation reduces largely the isolation area without sacrificing too much active area for capping the trench comers using the capping-oxide layer 301b. However, it is apparently seen from FIG. 1B and FIG. 2B that the heavily-doped source and drain regions occupy almost 70% of the active area and most of them are prepared for contacts. As a consequence, the source and drain junction capacitances which may limit the switching speed or the operating frequency of devices can not be easily scaled according to the scaling rule and the generation/recombination currents due to the depletion regions of the source and drain junctions become one of the major sources of device leakage currents. Moreover, the shallow source and drain junctions which are needed to reduce the short-cannel effects become a challenge for contact technology without producing the contact-induced defects.
It is therefore a first objective of the present invention to substantially reduce the area of the heavily-doped source and drain regions of a device in the active region, so that the junction capacitances of the heavily-doped source and drain regions with respect to the semiconductor substrate in the active region are reduced accordingly. As a result, high-speed and high-frequency operations of devices of the present invention for manufacturing integrated-circuits can be expected. Since the reduced heavily-doped source and drain regions are resided on the trench-isolation regions, it is therefore a second objective of the present invention to substantially reduce the generation/recombination currents in the depletion regions of the heavily-doped source and drain junctions. Moreover, the heavily-doped source and drain regions resided on the trench-isolation regions are the silicided conductive semiconductor layers for contacts or interconnections, it is a third objective of the present invention to eliminate the contact-induced source and drain junction failure or leakage currents. In addition, the effective area of a device is much reduced, it is therefore a fourth objective of the present invention to offer high-density devices for manufacturing high-density integrated-circuits.
Methods of fabricating a semiconductor device structure having low source and drain junction capacitances and low junction leakage currents are disclosed by the present invention, in which the major portions of the heavily-doped source and drain regions of a device in the active region are implemented in a self-aligned manner over the trench-isolation region by using highly-conductive silicided polycrystalline or amorphous-semiconductor layers. The device structure of the present invention exhibits several remarkable features as compared to those of existing device structure. The first feature of the present invention is very low source and drain junction capacitances, so much higher switching speed or operating frequency can be obtained by using a device structure of the present invention for manufacturing high-density integrated-circuits. The second feature of the present invention is very small area for the depletion regions of the heavily-doped source and drain junctions, the generation/recombination currents in the depletion regions of the source and drain junctions and the conventional diffusion current can be much reduced, so ultra-low standby leakage current can be obtained for manufacturing high-density integrated-circuits. The third feature of the present invention is that the contacts of the source and drain regions of a device are resided on the trench-isolation region, the contact-induced defects or spikings for shallow source and drain junctions can be eliminated, the elaborate contact technologies are not required and the yield problems of integrated-circuits manufacturing due to the excess leakage current or junction failures are eliminated. The fourth feature of the present invention is that the effective area occupied by each device of the present invention is much smaller as compared to that of existing devices, integrated-circuits of much higher density can be manufactured by the present invention. As a consequence, the present invention can be used to manufacture integrated-circuits with high-density, high-speed and ultra-low standby leakage current.